(1) Field of the Invention
The present invention relates to the manufacture of ultra large scale integrated (ULSI) circuit chips in general, and in particular, to forming interconnects in a semiconductor substrate by using a borderless contact process.
(2) Description of the Related Art
Interconnections between devices and other conductive layers separated from each other by insulating layers horizontally disposed in semiconductor substrates are made by vertical connections that are formed in the insulating layers. The vertical connections that contact the devices formed in the substrate are referred to as contacts while the vertical connections that connect the upper metal layers are referred to as vias. In either case, the challenge is to be able to make the vertical connections such that they lie squarely over the features that they are to connect. Any misalignment between the vertical connections and the features that they are to connect can cause defects and reliability problems. Thus, in order to assure that a vertical connection does fall within the intended feature, the features are made larger than required. The area by which the feature is made larger is called a border around the vertical contact hole or via hole. This increased area then impacts the packing density of the features, and hence the number of circuits that can be integrated into a semiconductor substrate. It is desirable, therefore, to eliminate the borders of prior art, that is, to form borderless contacts and vias in order to increase the integration levels of integrated circuits, and benefit from the attendant improvements in performance for the reasons known in the art. This invention discloses a method of forming such borderless contacts and vias.
As the very large and ultra large scale integration (VLSI and ULSI) of circuits progresses to even smaller feature sizes less than half micron, one of the most important challenges to be overcome is the level-to-level alignment in lithography, especially that of complex structures of metal line and contact interconnects. The packing density of circuits is limited to a large extent by how closely the interconnect metal between circuits can be formed without encroaching on each other. As is well known in the field, the limits are dictated by design rules that govern the separation of one level of contact from another, and by design rules for nesting tolerance or for borders used around contacts. The present invention discloses a method for forming interconnects without borders. The method is equally applicable to either a metal plug formed through a contact hole over a device in a substrate, or through a via hole connecting two metal layers at different levels in a substrate. It will be known to those skilled in the art that contacts refer to an interconnect which interconnects a source-drain device region, salicide of polysilicon to metal, while vias refer to an interconnect which connects metal to metal.
The effect on packing density of borders around contacts is well illustrated by S. M. Sze, et al., in an article published in ULSI Technology. FIGS. 1a, 2c in the drawings, adapted from Sze, show a gain of more than 62% in the packing area in going from a contact having borders to no borders. FIG. 1a shows fully bordered, staggered vias (23) and (33) formed between metal layers (20) and (30. Metal layers have been patterned to form metal lines (27) at the lower level and metal lines (37) on the upper level. Single and double primed reference numerals (27) and (37) refer to other metal lines at the respective levels (20) and (30), respectively. Via (33) on the upper level has border (31) and via (23) on the lower level has its border (21). Ideally, the pitch between metal lines such as (35) for the upper metal lines and (25) for the lower metal lines, is determined by the minimum line and space dimensions that can be patterned using the most recent advances in lithographic techniques. In practice, line pitch is also limited by the via size and the underlying metal pad size forming the border around the via, such as (31) and (21). It will be known by those skilled in the art that a border around a via is needed, for otherwise, grooves would be etched into the underlying insulating layer during the via-etch step, thus causing a thinning of the next level of metal deposited over the via. The minimum dimension by which the metal pad must frame the via, that is, form a border, is dependent on the misalignment tolerances of the lithography step.
Furthermore, the slope of the via wall must be taken into account when determining the minimum pitch between vias. Sloped walls are needed so that the vias can be filled more easily with metal, and without any voids inside the via holes. Also, appropriate slope is needed for adequate metal coverage over the step of the edge of the via hole when physical vapor deposition is employed. The step coverage is in turn dependent upon the aspect ratio, that is, depth over the width of the via hole. A cross-sectional view of vias (55) and (65) with sloped walls (57) and (67), respectively, is shown in FIG. 1b. It will be noted that the more is the slope of the via wall, the larger the border must be for the metal pad over the lower via to insure full coverage of the via.
It is also noted that the vias of FIG. 1a and FIG. 1b are formed laterally with respect to each other. That is, they are staggered rather than being stacked on top of one another as shown in FIG. 1c. The pitch between staggered vias can be reduced if the borders around the vias can also be reduced. The borders can be reduced if the slope of the walls can be reduced. The slope can be reduced if the holes can be filled properly with walls approaching vertical orientation. As is known in the art, forming metal plugs, such as tungsten plugs, in via holes separate from forming metal lines makes vertical vias possible. Plug forming methods are advantageous also in filling contact or via holes of different cross-sectional areas, though they may not fill the openings up to the top. This is shown by reference numerals (75) and (85) in FIG. 1c where vias (73) and (83) have more steeply sloped walls, and they span, respectively, insulation layers (70) and (80).
Vias with vertical walls, and wit no borders, can also be made, as disclosed later in this invention and as depicted in FIG. 2a. In FIG. 2a, vertical vias (93) and (103) are formed in insulating layers (90) and (100), respectively, connecting two metal layers (97) and (107). Thus, the minimum distance, such as (25) and (35) in FIG. 2b, between adjacent metal lines, is reduced since the vias have no slope. Secondly, the borders are no longer needed, since plugs (23), (33) in the completely filled vias provide ample overetch protection to underlying metal structures without mask coverage, as it will be appreciated by those skilled in the art. Even with borderless vias only, then, there is substantial reduction in the area occupied by these vias as shown in FIG. 2b in comparison with vias with borders of FIG. 1a. Hence, the pitch (35') between adjacent lines (37) and (37') can be reduced . The line pitch can be further reduced if the vias are stacked on top of one another as shown in FIG. 2c where upper vias (23), (23') and (23") are stacked on top of lower vias (33), (33') and (33"), thus significantly reducing upper metal line pitch from (35) to (35"), and lower metal line pitch from (25) to (25"). Hence, significant gains in packing density can be achieved with stacked and borderless contacts or vias.
However, the practice of stacking contacts and borderless contacts is still in its infancy, as observed by Sze in the earlier Reference. Conventionally, the metal layers and the interconnecting layers are formed separately, and serially. First, a first blanket metal is deposited on a first insulating layer and electrical lines are formed by subtractive etching of the metal through a first mask. A second insulating layer is formed over the first metallized layer, and the second insulating layer is patterned with contact or via holes using a second mask. The holes are then filled with metal, thus forming metal columns, or plugs, contacting the first metal layer. A second blanket metal layer is formed over the second insulating layer containing the columnar plugs which now connect the upper second metal layer with the lower first metal layer. The second metal layer is next patterned with another mask to form a set of new metal lines, and the process is repeated as many times as it is needed to fabricate a semiconductor substrate. With this conventional process, lithographic alignment tolerances must be held very tight in order to form reliable borderless contacts or vias.
Some of the difficulties in forming borderless contacts have been addressed in prior art. For example, Barber, et al., in U.S. Pat. No 4,966,870 show a method for making borderless contacts through an insulating layer to active regions of a semiconductor device. After deposition of a silicon nitride layer and an insulation glass layer on a substrate coating semiconductor devices, the contact windows are etched. The windows are etched through the glass layer with BCl.sub.2 or CHF.sub.3 /CF.sub.4 etch gases. Next, the windows are etched through the silicon nitride with CH.sub.3 F or O.sub.2 /.CHF.sub.3 gases. Mu, et al., show several methods of forming an interconnect on a semiconductor substrate by using an etch-stop layer in U.S. Pat. No. 5,612,254. Chung, on the other hand, teaches, in U.S. Pat. No. 5,656,543, the fabrication of integrated circuits with borderless vias with the use of an etch-stop spacer whereby even if a via is misaligned with a metal line, a portion of the via not enclosed by the metal is enclosed by the etch-stop spacer. Givens, et al., disclose in U.S. Pat. No. 5,605,862 a process for making low-leakage contacts using differently doped layers. The present invention discloses a still another method of forming borderless contacts and vias with the attendant advantages of eliminating one photoresist mask, self-alignment capability, and easy photoresist stripping and cleaning, and hence, an over-all increase in manufacturability of borderless interconnects as will be apparent in the embodiments of the invention.